The present invention relates generally to data processing systems and more particularly to data processing systems which have a plurality of interrupt sources in response to an interrupt request form which interrupt service is provided.
There are various types of interrupt processing systems in the prior art which are coupled to provide interrupt service in response to an interupt signal received from any one of a number of sources such as peripherals connected on an input/output bus. Typically, the procedure followed for servicing interrupts from such peripherals first requires identifying the interrupting peripheral, next requesting the status of the peripheral and then providing the status. This procedure is relatively slow and in certain types of systems where interrupt routines are executed frequently, the acknowledge routine time may pose serious speed restraints on the total system. In one such interrupt system, as indicated in U.S. Pat. No. 3,881,174, the interrupt processing apparatus includes a computer which allows a peripheral, upon receiving an acknowledgement from a computer of an interrupt request which the peripheral previously generated, to simultaneously provide the computer with its address and status thereby shortening the time required for the interrupt routine. Thus the time saved in processing interrupt requests is very important particularly where such interrupt requests occur frequently, not only from peripherals coupled to the computer, but also from internal interrupt sources such as those which may be generated by computer programs executing in the computer. The processing of such interrupts within the computer in order to enable interrupt service must therefore be capable of distinguishing different types of interrupts as well as the priority or interruptability level associated therewith and in response thereto provide a mechanism for enabling such interrupt service in as short a time as possible.
It is accordingly one of the principal objects of the present invention to provide a computer system which includes an improved interrupt processing system.